METHOD AND APPARATUS FORMING COPPER (Cu) OR ANTIMONY (Sb) DOPED ZINC TELLURIDE AND CADMIUM ZINC TELLURIDE LAYERS IN A PHOTOVOLTAIC DEVICE

ABSTRACT

A method and apparatus for an amount of Cu or Sb dopant incorporated into a zinc-based layer as the layer is being formed. The layer is formed over a coated substrate using an electrochemical deposition (ECD) process. In the ECD process, the bias voltage and plating solution composition may be systematically changed during the electrochemical deposition process to change the amount of Cu or Sb dopant incorporated into the plated layer.

This application is a divisional of U.S. patent application Ser. No.14/136,630, filed Dec. 20, 2013, which claims the benefit of priority ofU.S. Provisional Patent Application No. 61/746,877, filed Dec. 28, 2012,entitled: “Method and Apparatus for Forming Copper (Cu) or Antimony (Sb)Doped Zinc Telluride Layers in a Photovoltaic Device” the entirety ofwhich is incorporated by reference herein.

FIELD OF THE INVENTION

Disclosed embodiments relate generally to methods and apparatuses formanufacturing photovoltaic devices including photovoltaic cells andphotovoltaic modules, and more particularly, to a method and apparatusfor forming and controlling the composition of Cu and Sb doped zinctelluride and cadmium zinc telluride thin film layers during formationof photovoltaic devices.

BACKGROUND OF THE INVENTION

Photovoltaic devices are becoming increasingly popular for providingrenewable energy. FIG. 1 shows one example of a photovoltaic device 100,which can be formed by depositing sequential thin film layers on asubstrate 110. The photovoltaic device 100 may include a TCO stack 170formed over the substrate 110, semiconductor layers 180 formed over theTCO stack 170, a back contact 155 formed over semiconductor layers 180and a back support 160 formed over the back contact 155.

Generally, the substrate 110 is the outermost layer of a completedphotovoltaic device 100 and, in use, may be exposed to a variety oftemperatures and forms of precipitation, such as rain, snow, sleet, andhail. The substrate 110 may also be the first layer that incident lightencounters upon reaching the photovoltaic device 100. It is thereforedesirable to select a material for the substrate 110 that is bothdurable and highly transparent. For these reasons, the substrate 110 mayinclude, for example, borosilicate glass, soda lime glass, or floatglass.

The TCO stack 170 may include a barrier layer 115 formed on thesubstrate 110 for preventing sodium diffusion from the substrate 110into the photovoltaic device. The barrier layer 115 may be formed of,for example, silicon nitride, silicon oxide, aluminum-doped siliconoxide, boron-doped silicon nitride, phosphorus-doped silicon nitride,silicon oxide-nitride, or any combination or alloy thereof. The TCOstack 170 further includes a TCO layer 120 formed on the barrier layer115. The TCO layer 120 functions as the first of two electrodes of thephotovoltaic device 100 and may be formed of, for example, fluorinedoped tin oxide, cadmium stannate, or cadmium tin oxide. In addition,the TCO stack 170 includes a buffer layer 125 formed on the TCO layer120 to provide a smooth surface for semiconductor material deposition.The buffer layer 120 may be formed of, for example, tin oxide (e.g., atin (IV) oxide), zinc tin oxide, zinc oxide, zinc oxysulfide, and zincmagnesium oxide. It is possible to omit one or both of the barrier layer115 and buffer layer 120 in the TCO stack 170 if desired.

Back contact 155 functions as the second of the two electrodes and maybe made of one or more highly conductive materials, for example,molybdenum, aluminum, copper, silver, gold, or any combination thereof,providing a low-resistance ohmic contact. TCO layer 120 and back contact155 are used to transport photocurrent away from photovoltaic device100. Back support 160, which may be glass, is formed over back contact155 to protect, together with substrate 110, photovoltaic device 100from external hazards.

The semiconductor layers 180 may include a semiconductor window layer130, for example, a cadmium sulfide layer, and a semiconductor absorberlayer 140, for example, a cadmium telluride layer. The semiconductorlayers 180 may further optionally include a transition semiconductorlayer 145, for example, a cadmium zinc telluride layer, and asemiconductor reflector layer 150, for example, a zinc telluride layer.The semiconductor window layer 130 allows the penetration of solarradiation to the semiconductor absorber layer 140 which then convertssolar energy to electricity through the formation of minority electroncarriers. Specifically, semiconductor materials, like any other solids,have an electronic band structure consisting of a valence band, aconduction band and a band gap separating them. When an electron in thevalence band acquires enough energy to jump over the band gap and reachthe conduction band, it can flow freely as current. Furthermore, it willalso leave behind an electron hole in the valence band that can flow asfreely as current. Carrier generation describes processes by whichelectrons gain energy and move from the valence band to the conductionband, producing two mobile carriers: an electron and a hole; whilerecombination describes processes by which a conduction band electronloses energy and re-occupies the energy state of an electron hole in thevalence band. In a p-type semiconductor material like the semiconductorabsorber layer 140, electrons are less abundant than holes, hence theyare referred to as minority electron carriers whereas holes are referredto as majority carriers.

During the conversion of solar energy to electricity at thesemiconductor absorber layer 140, some minority electron carrierspenetrate through the absorber layer 140 and may recombine with holecarriers, causing power dissipation inside the photovoltaic device 100,thereby reducing power conversion efficiency. Accordingly, optionalsemiconductor reflector layer 150 can be deposited over thesemiconductor absorber layer 140 to act as a barrier or reflectoragainst the minority electron carrier diffusion. The reflector layer 150is formed of a semiconductor material with electron affinity lower thanthat of the absorber layer 140, for example, zinc telluride (ZnTe),which forces electron carrier flow back toward the electron absorberlayer 140, minimizing minority electron diffusion. This is described inU.S. Provisional Patent Application 61/547,924, entitled “PhotovoltaicDevice And Method Of Formation,” filed on Oct. 17, 2011, the disclosureof which is incorporated herein by reference.

Although optional semiconductor reflector layer 150 reduces powerdissipation and increases power conversion efficiency in thephotovoltaic device 100, lattice mismatch may occur between thesemiconductor reflector layer 150 and the semiconductor absorber layer140, which can partially negate this benefit. In general, semiconductormaterials contain a lattice, or a periodic arrangement of atoms specificto a given material. Lattice mismatching refers to a situation whereintwo materials featuring different lattice constants (a parameterdefining the unit cell of a crystal lattice, that is, the length of anedge of the cell or an angle between edges) are brought together bydeposition of one material on top of another. In general, latticemismatch can cause film growth against the natural grain of the adjacentfilm, film cracking, and creation of point defects at the interfacebetween the two materials featuring the different lattice constants.

To reduce the effects of lattice mismatch between the semiconductorabsorber layer 140 and the semiconductor reflector layer 150, theoptional semiconductor transition layer 145, formed of a combination ofthe semiconductor absorber material and the semiconductor reflectormaterial, for example, a Cd(1-x)Zn(x)Te layer where 0<x<1, may be formedbetween the semiconductor absorber layer 140 and the semiconductorreflector layer 150. By virtue of its composition, the semiconductortransition layer 145 has a lattice constant between that of thesemiconductor absorber layer 140 and the semiconductor reflector layer150, which reduces lattice mismatch between the two layers and increasesthe electronic conversion efficiency of the photovoltaic device 100.

Forming the semiconductor reflector layer 150 and the semiconductortransition layer 145 in a photovoltaic device may be hindered by theintrinsic nature of the combined semiconductor materials that composethe two layers, for example, cadmium (Cd), zinc (Zn) and telluride (Te).Specifically, ZnTe and CdZnTe are highly resistive films, which cancause flaws to form in the semiconductor reflector layer 150 and/or thesemiconductor transition layer 145 as they are formed over othersemiconductor layers, for example, a cadmium telluride layer 140.Incorporating conductive dopant into the ZnTe and CdZnTe layers canincrease the conductivity and decrease the resistivity of these layers,which reduces the flaws that may occur during formation and provides theelectrical properties necessary for the layers to function in aphotovoltaic device. Accordingly, a method and apparatus forincorporating conductive dopant into zinc telluride and cadmium zinctelluride thin film layers during formation of photovoltaic devices isdesired.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a photovoltaic device having multiple thin filmlayers;

FIGS. 2A-2B are schematics of a zinc-based semiconductor layer formedover a partially completed photovoltaic device;

FIGS. 3A-3B illustrates two possible mole fraction profiles for CZTtransition layers in various photovoltaic device configurations;

FIG. 4 illustrates a schematic of an ECD unit for incorporating a dopantinto a zinc-based semiconductor layer as it is formed over a partiallycompleted photovoltaic device;

FIG. 5 illustrates a flow chart of an ECD plating process forincorporating a dopant into a zinc-based semiconductor layer as it isformed over a partially completed photovoltaic device;

FIG. 6 illustrates a flow chart of an ECD plating process where ECD biasvoltage is changed during the plating process to change the amount ofdopant incorporated into the zinc-based semiconductor layer as it isformed over a partially completed photovoltaic device;

FIG. 7 illustrates a schematic of an ECD system having two ECD units forincorporating a dopant into a zinc-based semiconductor layer as it isformed over a partially completed photovoltaic device;

FIG. 8 illustrates a flow chart of an ECD plating process forincorporating a dopant into a zinc-based semiconductor layer as it isformed over a partially completed photovoltaic device using multipleplating baths with different plating solutions.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and which illustratespecific embodiments of the invention. These embodiments are describedin sufficient detail to enable those of ordinary skill in the art tomake and use them. It is also understood that structural, logical, orprocedural changes may be made to the specific embodiments disclosedherein without departing from the spirit or scope of the invention.

Disclosed herein are embodiments of a method and apparatus forincorporating and controlling an amount of conductive dopant, such as Cuor Sb dopant, incorporated into zinc-based semiconductor layers as thelayers are being formed over a partially completed photovoltaic device.To form the layers, an electrochemical deposition (ECD) system is used.In ECD systems, a plating solution is used that contains materials thatmake up the layer to be formed by the ECD process. By adding a dopantinto the plating solution along with the layer materials, the platedlayer will be doped in-situ during its formation. This is a ratherefficient method of doping layers. The method increases control over thedopant concentration throughout the doped zinc-based semiconductorlayer. It also eliminates any need for additional annealing steps, whichat times may damage previously formed layers of the photovoltaic device.

The method may further include, if desired, systematically changing, ina step-wise or gradual fashion, one, a few or all variables in a set ofECD variables while forming the zinc-based layers. Systematicallychanging the ECD variables creates a controlled step-wise or gradualchange in the amount of dopant that will be incorporated into thezinc-based layers as they get farther from the initial depositionsurface of the partially completed photovoltaic device.

FIG. 2A illustrates a zinc-based semiconductor layer 210 formed over apartially completed photovoltaic device 200A. The partially completedphotovoltaic device 200A includes a substrate 110 and thin film layers115, 120, 125, 130, 140 deposited sequentially thereon as described inFIG. 1. The doped zinc-based semiconductor layer 210 may be formed onthe semiconductor absorber layer 140. The layer, in this particularexample, may be a Cu or Sb doped cadmium zinc telluride (Cu:CZT orSb:CZT) layer 145 or a Cu or Sb doped zinc telluride reflector layer(Cu:ZnTe or Sb:CZT) 150 as described in reference to the examplephotovoltaic device 100 shown in FIG. 1.

The layer being formed may be a transition layer. A transition layer isa layer in which the concentration of an element/material transitionsfrom one concentration of an element at one surface of the layer to adifferent concentration of the element at the other surface. In thiscase, if the Cu or Sb doped zinc-based semiconductor layer 210 is aCu:CZT or Sb:CZT transition layer 145, then the CZT portion of the layermay be formed of one or several Cd(1-x)Zn(x)Te layers where x definesany suitable number between 0 and 1 and the zinc/cadmium mole ratiochanges either step-wise, gradually or randomly as it gets farther fromthe semiconductor absorber layer 140.

FIGS. 3A and 3B illustrate two possible zinc/cadmium mole-fractionprofiles that can be used to form the transition layer 145. In FIG. 3A,a step-wise increase of a zinc mole-fraction in the CZT transition layer145 from 0 to 1 is used, whereas in FIG. 3B a gradual increase of thezinc mole-fraction is used. It should be noted that FIGS. 3A and 3B areonly examples of possible zinc/cadmium mole-fraction profiles and thatthe CZT transition layer 145 can have any desired mole-fraction profile.

If the Cu or Sb doped zinc-based semiconductor layer 210 is a Cu:ZnTe orSb:ZnTe reflector layer 150, then the Cu or Sb doped zinc-basedsemiconductor layer 210 may be formed on a partially completedphotovoltaic device 200A without a CZT transition layer 145, as shown inFIG. 2A or, alternatively, on a partially completed photovoltaic device200B having the CZT transition layer 145 as shown in FIG. 2B. Partiallycompleted photovoltaic device 200B may include a substrate 110 and thinfilm layers 115, 120, 125, 130, 140, 145 deposited sequentially on thesubstrate 110 as described in reference to the example photovoltaicdevice 100 shown in FIG. 1. The Cu or Sb doped zinc-based semiconductorlayer 210, which, in the embodiment shown in FIG. 2B is a Cu:ZnTe orSb:ZnTe reflector layer 150, may be deposited over the CZT transitionlayer 145.

FIG. 4 illustrates an ECD unit 405 for incorporating Cu or Sb dopant ina Cu or Sb doped zinc-based semiconductor layer 210 as it is formed overa partially completed photovoltaic device 200. It should be notedregarding all embodiments described herein, partially completedphotovoltaic device 200, as shown in FIG. 4, may refer to eitherpartially completed photovoltaic device 200A, as shown in FIG. 2A orpartially completed photovoltaic device 200B, as shown in FIG. 2B orsome other partially completed photovoltaic device structure. Referringto FIG. 4, ECD unit 405 may include a container 410, a heater 415,associated with, e.g., under, the container 410, and plating solution420 in the container 410. When contacted with plating solution 420,partially completed photovoltaic device 200 is electrically connected topower source 470, which may have a positive terminal and a negativeterminal. The partially completed photovoltaic device 200 is most oftenconnected to the negative terminal and acts as a cathode in the ECD unit405. A complementary electrode 460 which may be made of any appropriateelectrode material known in the art, for example, carbon, stainlesssteel, platinum or any inert material, is electrically connected to theother terminal of the power source 470 and serves as an anode in the ECDunit 405.

In use, the power source 470 supplies an external ECD bias voltageacross the partially completed photovoltaic device 200 and the platingsolution 420. The ECD bias voltage may be any predetermined bias voltagesuitable for ECD, for example, a bias voltage in the range of about −0.3V to about −10 V. It should be noted that the ECD bias voltagesdisclosed herein are cathodic voltages measured across the partiallycompleted photovoltaic device 200 and the complementary electrode 460and at the complementary electrode 460. In some embodiments, the ECDbias voltage may be in the range of about −0.6 V to −2 V. In otherembodiments, the ECD bias voltage may be in the range of about −0.9 Vand −1.5 V. The power source 470 may have a control unit 472, which maybe capable of changing the ECD bias voltage across the partiallycompleted photovoltaic device 200 and the plating solution 420 duringECD.

When an ECD bias voltage is applied across the partially completedphotovoltaic device 200 and the plating solution 420, solutes ofinterest are attracted from the plating solution 420 to the partiallycompleted photovoltaic device 200 and form a Cu or Sb doped zinc-basedsemiconductor layer 210 over the partially completed photovoltaic device200. The plating solution 420 may contain one or more Cu or Sb dopant,one or more complexing agents, which are compounds that chemicallyinteract with the dopant as the dopant is incorporated into the platedCu or Sb doped zinc-based semiconductor layer 210, and one or moresemiconductor solute(s) to form the Cu or Sb doped zinc-basedsemiconductor layer 210, all dissolved in any appropriate solvent, suchas water or a mixture of water and other water-soluble solvents.

The Cu or Sb dopant may be any soluble Cu or Sb containing compoundsthat can be reduced or incorporated into a semiconductor layer. Forexample, the Cu dopant may be copper sulfide, copper sulfate, copperchloride, copper fluoride, cooper nitrate, copper phosphate, or coppercitrate. The Sb dopant may be antimony sulfide, antimony sulfate,antimony chloride, antimony fluoride, antimony nitrate, antimonyphosphate or antimony citrate. The Cu or Sb dopant compounds may bedissolved in the plating solution 420 to form ions or electrolytes thatcan be reduced, oxidized, or deposited to be incorporated into theplated Cu or Sb doped zinc-based semiconductor layer 210. The dopantconcentration in plating solution 420 may be set based on the desiredcomposition of the layer. For example, in some embodiments, the platingsolution 420 may have Cu or Sb concentration in the range of about 0.01mM (millimolar) to about 10 M (molar). In other embodiments, the platingsolution 420 may have a Cu or Sb concentration in the range of about 1mM to about 100 mM. In other embodiments, plating solution 420 may havea Cu or Sb concentration in the range of about 5 mM to about 50 mM.

The complexing agents may be soluble compounds that coordinate orposition Cu or Sb dopant in the plating solution for incorporation intothe Cu or Sb doped zinc-based semiconductor layer 210 as it is plated onthe partially completed photovoltaic device 200. For example, thecomplexing agent may be citrate, phenathroline, thiocyanate, halides,pyridines, and their derivatives.

The semiconductor solutes may be any suitable material(s) for forming aplated Cu or Sb doped zinc-based semiconductor layer 210 over thepartially completed photovoltaic device 200. The solutes may bedissolved in plating solution 420 as ions or electrolytes that can bereduced, oxidized, or deposited to form a plated Cu or Sb dopedzinc-based semiconductor layer 210. For example, if the doped zinc-basedsemiconductor layer 210 is a Cu:ZnTe or Sb:ZnTe reflector layer 150, theplating solution 420 may include solutes of zinc (Zn) and telluride(Te). Alternatively, if the doped zinc-based semiconductor layer 210 isa Cu:CZT or Sb:CZT transition layer 145, the plating solution 420 mayinclude solutes of cadmium (Cd), zinc (Zn) and telluride (Te). Theconcentrations of each solute can be determined based on the desiredcomposition of the plated Cu or Sb doped zinc-based semiconductor layer210. For example, if the doped zinc-based semiconductor layer 210 is aCu:ZnTe or Sb:ZnTe reflector layer 150, an exemplary plating solution420 may have a zinc concentration in the range of about 0.1 M to about10 M and a telluride concentration in the range of about 0.1 M to about10 M. Alternatively, if the doped zinc-based semiconductor layer 210 isa Cu:CZT or Sb:CZT transition layer 145, the plating solution 420 mayhave a cadmium concentration of about 0.1 M to about 10 M, a zincconcentration in the range of about 0.1 M to about 10 M and a tellurideconcentration in the range of about 0.1 M to about 10 M. The platingsolution 420 may have a pH of about 0 to about 14. In some embodiments,plating solution 420 has a pH of about 1 to about 7, or about 2 to about4. In other embodiments, plating solution 420 has a pH of about 7 toabout 14, or about 9 to about 12. In still other embodiments, platingsolution 420 has a pH of about 5 to about 9, or about 6 to about 8.

ECD unit 405 can function at a predetermined temperature, for example,heater 415 may heat the plating solution 420 to a temperature of about10° C. to about 100° C., about 10° C. to about 50° C., about 15° C. toabout 30° C., about 25° C., or room temperature. During the platingprocess, power source 470 may generate an ECD bias voltage for apredetermined length of time, including about 5 seconds to about 100,000seconds, about 50 seconds to about 7,500 seconds, about 100 seconds toabout 750 seconds, and about 100 seconds to about 500 seconds. Thelength of time that the ECD bias voltage is applied across the partiallycompleted photovoltaic device 200 and the plating solution 420 maydetermine the thickness of the plated Cu or Sb doped zinc-basedsemiconductor layer 210. Accordingly, the length of time can be chosento be sufficient to form the doped zinc-based semiconductor layer 210over the partially completed photovoltaic device 200 having anydesirable thickness, for example, between about 0 nm and about 3000 nm.In some embodiments, the doped zinc-based semiconductor layer 210 mayhave a thickness of between about 5 nm and 500 nm. In other embodiments,the doped zinc-based semiconductor layer 210, may have a thickness ofbetween about 10 nm to about 100 nm.

After the plated Cu or Sb doped zinc-based semiconductor layer 210 iscompletely formed over the partially completed photovoltaic device 200,the partially completed photovoltaic device 200 may be removed fromplating solution 420. Partially completed photovoltaic device 200 maythen be washed, and additional layers may be formed over the Cu or Sbdoped zinc-based semiconductor layer 210 formed on the partiallycompleted photovoltaic device 200 if desired.

It is important to recognize that the ECD bias voltage generated by thepower source 470 and the composition of the plating solution 420 arevariables in the ECD process that may determine the amount of Cu or Sbdopant incorporated into the Cu or Sb doped zinc-based semiconductorlayer 210 as it is formed on the partially completed photovoltaic device200. Certain conditions have been found to incorporate a high percentageof Cu or Sb dopant into a plated layer, for example, about 3% to about30% incorporation of the Cu dopant or about 12% to about 80%incorporation of the Sb dopant from the plating solution 420, whileother conditions have been found to incorporate a low percentage of Cuor Sb dopant into a plated layer, for example, about 0.0001% to about 3%incorporation of the Cu dopant or about 0.5% to about 12% incorporationof the Sb dopant from the plating solution 420, during ECD. Referringspecifically to ECD bias voltage, performing the ECD process at a biasvoltage of, for example, about −0.9 V incorporates a high percentage ofCu or Sb dopant into a plated layer, for example, about 3% to about 30%incorporation of the Cu dopant or about 12% to about 80% incorporationof the Sb dopant. Conversely, performing the ECD process at a biasvoltage of, for example, about −1.1 V incorporates a low percentage ofCu or Sb dopant into a plated layer, for example, about 0.0001% to about3% incorporation of the Cu dopant or about 0.5% to about 12%incorporation of the Sb dopant.

Referring specifically to plating solution composition, theconcentration of Cu or Sb dopant in the plating solution 420 has adirect correlation to the amount of dopant incorporated into the platedCu or Sb doped zinc-based semiconductor layer 210 formed over thepartially completed photovoltaic device 200. If the concentration ofdopant in the plating solution 420 is low, for example, 0.01 mM to about100 mM, than the percent of dopant incorporated into the plated Cu or Sbdoped zinc-based semiconductor layer 210 will be low, for example, about0.0001% to about 3% incorporation of the Cu dopant or about 0.5% toabout 12% incorporation of the Sb dopant. Conversely, if theconcentration of dopant in the plating solution 420 is high, forexample, 100 mM to about 10 M, than the amount of dopant incorporatedinto the plated Cu or Sb doped zinc-based semiconductor layer 210 willbe high, for example, about 3% to about 30% incorporation of the Cudopant or about 12% to about 80% incorporation of the Sb dopant.

FIG. 5 illustrates a flow chart of an ECD plating process 500 with steps511-516, where an ECD unit 405, as shown in FIG. 4, may be used toincorporate Cu or Sb dopant into a Cu or Sb doped zinc-basedsemiconductor layer 210 as it is formed on a partially completedphotovoltaic device 200 and where the ECD bias voltage is used toestablish the amount of dopant incorporated into the plated layer. Instep 511, a plating solution 420 is prepared, which includes a solvent,for example, water, a Cu or Sb dopant compound dissolved in the solvent,a complexing agent, for example, citrate, dissolved in the water and azinc-based semiconductor solute mixture dissolved in the water. To forma Cu or Sb doped zinc-based semiconductor layer 210 that is a Cu:ZnTe orSb:ZnTe reflector layer 150, the zinc-based semiconductor solute mixturemay include, for example, zinc, and telluride ions or electrolytes, as asolute dissolved in the solvent, in a predetermined ratio for depositionof a Cu:ZnTe or Sb:ZnTe reflector layer 150. To form a Cu or Sb dopedzinc-based semiconductor layer 210 that is a Cu:CZT or Sb:CZT transitionlayer 145, the zinc-based semiconductor solute mixture may include, forexample, cadmium, zinc, and telluride ions or electrolytes, as a solutedissolved in the solvent, in a predetermined ratio for deposition of aCu:CZT or Sb:CZT transition layer 145. In step 512, a heater 415 heatsthe plating solution 420 to a predetermined temperature for depositionof the Cu or Sb doped zinc-based semiconductor layer 210, for example, atemperature in the range of about 10° C. to about 100° C. In step 513, apartially completed photovoltaic device 200 is contacted with the heatedplating solution 420 in container 410. In step 514, power source 470generates an ECD bias voltage across partially completed photovoltaicdevice 200 and plating solution 420. The ECD bias voltage may be apredetermined bias voltage in the range of about −0.3 V to about −10 Vand may be set based on the desired amount of the Cu or Sb dopant. Forexample, the ECD bias voltage may be set at about −0.9 V to incorporatea high percentage of Cu or Sb dopant into the plated layer, for example,about 3% to about 30% incorporation of the Cu dopant or about 12% toabout 80% incorporation of the Sb dopant. Alternatively, the ECD biasvoltage may be set at about −1.1 V to incorporate a low percentage of Cuor Sb dopant into the plated layer, for example, about 0.0001% to about3% incorporation of the Cu dopant or about 0.5% to about 12%incorporation of the Sb dopant. In step 515, the ECD bias voltage may beapplied for a predetermined period of time, for example, about 5 secondsto about 100,000 seconds, to plate the Cu or Sb doped zinc-basedsemiconductor layer 210 on the partially completed photovoltaic device200. In step 516, the partially completed photovoltaic device 200 withthe newly plated Cu or Sb doped zinc-based semiconductor layer 210 isremoved from the plating solution 420. It should be noted that the steps511-516 shown in FIG. 5 describe the steps in ECD plating process 500,but do not necessarily indicate any particular order or sequence ofsteps.

ECD unit 405 may also be operated by systematically changing the ECDbias voltage during the predetermined time allotted for plating the Cuor Sb doped zinc-based semiconductor layer 210, which changes the amountof Cu or Sb dopant incorporated into the Cu or Sb doped zinc-basedsemiconductor layer 210 as it gets farther from the partially completedphotovoltaic device 200. Generally speaking, the initial platingconditions may be set such that either a high or low amount of thedopant is initially incorporated into the Cu or Sb doped zinc-basedsemiconductor layer 210 and then the ECD plating condition may bechanged in a stepwise or gradual fashion during the plating process sothat the amount of Cu or Sb dopant incorporated into the plated Cu or Sbdoped zinc-based semiconductor layer 210 either increase or decreases asit gets father from the partially completed photovoltaic device 200.

It should be noted that when the Cu or Sb doped zinc-based semiconductorlayer 210 being formed in the ECD plating process is a Cu:CZT or Sb:CZTtransition layer 145, systematically changing the ECD bias voltageduring the plating process also changes the semiconductor composition ofthe Cu:CZT or Sb:CZT transition layer 145 as it is plated. Specifically,changing the ECD bias voltage changes the ratio of zinc solutes tocadmium solutes in the plated layer. For example, performing the ECDprocess at a bias voltage of, for example, about −0.9 V favorsincorporation of cadmium solutes into the plated layer overincorporation of zinc solutes. Conversely, performing the ECD process ata voltage of, for example, about −1.2 V favors incorporation of zincsolutes into the plated layer over incorporation of cadmium solutes.Thus, systematically changing the ECD bias voltage during thepredetermined time will change the amount of Cu or Sb dopantincorporated into the Cu:CZT or Sb:CZT transition layer 145 and it willchange the zinc solute to cadmium solute ratio in the Cu:CZT or Sb:CZTtransition layer 145.

FIG. 6 illustrates a flow chart of an ECD plating process 600 with steps611-616, where and ECD unit 405, as shown in FIG. 4, may be used toincorporate Cu or Sb dopant into a Cu or Sb doped zinc-basedsemiconductor layer 210 as it is formed on a partially completedphotovoltaic device 200 and where changing the ECD bias voltage duringthe plating process is used to change the amount of dopant incorporatedinto the Cu or Sb doped zinc-based semiconductor layer 210 as it getfarther from the partially completed photovoltaic device 200. In step611, a plating solution 420 is prepared, which includes a solvent, forexample, water, a Cu or Sb dopant compound dissolved in the solvent, acomplexing agent, for example, citrate, dissolved in the water and azinc-based semiconductor solute mixture dissolved in the water. To forma Cu or Sb doped zinc-based semiconductor layer 210 that is a Cu:ZnTe orSb:ZnTe reflector layer 150, the zinc-based semiconductor solute mixturemay include, for example, zinc, and telluride ions or electrolytes, as asolute dissolved in the solvent, in a predetermined ratio for depositionof a Cu:ZnTe or Sb:ZnTe reflector layer 150. To form a Cu or Sb dopedzinc-based semiconductor layer 210 that is a Cu:CZT or Sb:CZT transitionlayer 145, the zinc-based semiconductor solute mixture may include, forexample, cadmium, zinc, and telluride ions or electrolytes, as a solutedissolved in the solvent, in a predetermined ratio for deposition of aCu:CZT or Sb:CZT transition layer 145. In step 612, a heater 415 heatsthe plating solution 420 to a predetermined temperature for depositionof the Cu or Sb doped zinc-based semiconductor layer 210, for example, atemperature in the range of about 10° C. to about 100° C. In step 613, apartially completed photovoltaic device 200 is contacted with the heatedplating solution 420 in container 410. In step 614, power source 470generates an initial ECD bias voltage across partially completedphotovoltaic device 200 and plating solution 420. The initial ECD biasvoltage may be a predetermined bias voltage in the range of about −0.3 Vto about −10 V and may be set based on the desired initial amount of Cuor Sb dopant. For example, the ECD bias voltage may be set at about −0.9V to incorporate a high percentage of Cu or Sb dopant into the platedlayer, for example, about 3% to about 30% incorporation of the Cu dopantor about 12% to about 80% incorporation of the Sb dopant. Alternatively,the ECD bias voltage may be set at about −1.1 V to incorporate a lowpercentage of Cu or Sb dopant into the plated layer, for example, about0.0001% to about 3% incorporation of the Cu dopant or about 0.5% toabout 12% incorporation of the Sb dopant. Again, it should be noted,that if the doped zinc-based semiconductor layer 210 being plated is aCu:CZT or Sb:CZT transition layer 145, then performing the ECD processat a bias voltage of about −0.9 V favors incorporation of cadmiumsolutes into the plated layer over incorporation of zinc solutes.Conversely, performing the ECD process at a voltage of, for example,about −1.2 V favors incorporation of zinc solutes into the plated layerover incorporation of cadmium solutes.

In step 615, the control unit 472 changes the applied ECD bias voltagefrom the initial ECD bias voltage to an ending ECD bias voltage in orderto modulate dopant incorporation percentage. If a low to high dopantconcentration profile is desired, the initial ECD bias voltage can beset relatively high, for example −1.1 V, to favor lower dopantincorporation at the beginning of the plating, for example, about0.0001% to about 3% Cu dopant incorporation or about 0.5% to about 12%incorporation of the Sb dopant. If a high to low dopant concentrationprofile is desired, the initial ECD bias voltage can be set relativelylow, for example −0.3 V, to favor higher dopant incorporation at thebeginning of the plating, for example, about 3% to about 30%incorporation of the Cu dopant or about 12% to about 80% incorporationof the Sb dopant. The control unit 472 may then change the initial ECDbias voltage to an ending ECD bias voltage that favors the oppositedopant incorporation in a step-wise, gradual or random fashion. In step616, the partially completed photovoltaic device 200 with the newlyplated Cu or Sb doped zinc-based semiconductor layer 210 is removed fromthe plating solution 420. Again, it should be noted that the steps611-616 shown in FIG. 5 describe the steps in ECD plating process 800,but do not necessarily indicate any particular order or sequence ofsteps.

In other embodiments, it may be desirable to use multiple platingsolutions having different compositions to change the amount of Cu or Sbdopant that is incorporated into the Cu or Sb doped zinc-basedsemiconductor layer 210 during the ECD process. FIG. 7 shows an ECDsystem 700 which may include multiple ECD units 705, 707. Although twoECD units are shown in FIG. 7, any number of ECD units may be used. Asdescribed with reference to the single ECD unit 405 shown in FIG. 4,first and second ECD units 705, 707 may include first and secondcontainers 710, 712, first and second heaters 715, 717 associated with,e.g., positioned under, the first and second containers 710, 712respectively and first and second plating solutions 720, 722 in firstand second containers 710, 712 respectively. First and second platingsolutions 720, 722 may have different Cu or Sb dopant concentrations.Accordingly, first and second ECD units 705, 707 may be used incombination to form a Cu or Sb doped zinc-based semiconductor layer 210over a partially completed photovoltaic device 200 with a differentamount of Cu or Sb dopant incorporated into the Cu or Sb dopedzinc-based semiconductor layer 210 as it moves away from the partiallycompleted photovoltaic device 200.

When contacted with the first plating solution 720, partially completedphotovoltaic device 200 is electrically connected to a first powersource 770, which may have a positive terminal and a negative terminal.The partially completed photovoltaic device 200 is electricallyconnected to the negative terminal of the first power source 770 and mayact as a cathode in first ECD unit 705. A first complementary electrode760, which may be made of any appropriate electrode material known inthe art, is electrically connected to the positive terminal of the firstpower source 770 and may act as an anode in the first ECD unit 705. Inuse, the first power source 770 generates an external ECD bias voltageacross partially completed photovoltaic device 200 and first platingsolution 720. The first power source 770 may have a first control unit772, which may be capable of changing the ECD bias voltage across thepartially completed photovoltaic device 200 and the first platingsolution 720 during ECD. Solutes from first plating solution 720 areattracted to partially completed photovoltaic device 200 and form afirst portion of the Cu or Sb doped zinc-based semiconductor layer 210over the partially completed photovoltaic device 200. Then the partiallycompleted photovoltaic device 200 is removed from first plating solution720 and contacted with second plating solution 722.

When contacted with the second plating solution 722, partially completedphotovoltaic device 200 is electrically connected to a second powersource 774, which may have a positive terminal and a negative terminal.The partially completed photovoltaic device 200 is electricallyconnected to the negative terminal of the second power source 774 andmay act as a cathode in the second ECD unit 707. A second complementaryelectrode 762, which may be made of any appropriate electrode materialknown in the art, is electrically connected to the positive terminal ofthe second power source 774 and may act as an anode in the second ECDunit 705. In use, the second power source 774 generates an external ECDbias voltage across partially completed photovoltaic device 200 andsecond plating solution 722. The second power source 774 may have asecond control unit 776, which may be capable of changing the ECD biasvoltage across the partially completed photovoltaic device 200 and thesecond plating solution 722 during ECD. Solutes from second platingsolution 722 are attracted to partially completed photovoltaic device200 and form a second portion of the Cu or Sb doped zinc-basedsemiconductor layer 210 over the partially completed photovoltaic device200. Then the partially completed photovoltaic device 200 is removedfrom the second plating solution 722.

FIG. 8 illustrates a flow chart of an ECD plating process 800 with steps811-819, where an ECD system 700, as shown in FIG. 7, may be used tochange the amount of Cu or Sb dopant incorporated into a Cu or Sb dopedzinc-based semiconductor layer 210 as it is plated using platingsolutions with different compositions. In step 811, a first platingsolution 720 is prepared, which may include a solvent, for example,water, a Cu or Sb dopant compound dissolved in the solvent, a complexingagent, for example, citrate, dissolved in the water and a zinc-basedsemiconductor solute mixture dissolved in the water. To form a Cu or Sbdoped zinc-based semiconductor layer 210 that is a Cu:ZnTe or Sb:ZnTereflector layer 150, the zinc-based semiconductor solute mixture mayinclude, for example, zinc, and telluride ions or electrolytes, as asolute dissolved in the solvent, in a predetermined ratio for depositionof a Cu:ZnTe or Sb:ZnTe reflector layer 150. To form a Cu or Sb dopedzinc-based semiconductor layer 210 that is a Cu:CZT or Sb:CZT transitionlayer 145, the zinc-based semiconductor solute mixture may include, forexample, cadmium, zinc, and telluride ions or electrolytes, as a solutedissolved in the solvent, in a predetermined ratio for deposition of aCu:CZT or Sb:CZT transition layer 145. The dopant concentration in thefirst plating solution 720 may be set based on whether a high or lowamount of dopant is intended to be incorporated into the plated firstportion of the Cu or Sb doped zinc-based semiconductor layer 210. If alow percentage of Cu or Sb dopant is desired to be incorporated into thefirst portion of the plated Cu or Sb doped zinc-based semiconductorlayer 210, then the Cu or Sb dopant concentration in the first platingsolution 720 may be, for example, in the range of about 0.01 mM to about100 mM, which will result in about 0.0001% to about 3% incorporation ofthe Cu dopant or about 0.5% to about 12% incorporation of the Sb dopantinto the first portion of the plated Cu or Sb doped zinc-basedsemiconductor layer 210 during a first portion of the plating process.If a high percentage of Cu or Sb dopant is desired to be incorporatedinto the first portion of the plated Cu or Sb doped zinc-basedsemiconductor layer 210, than, for example, the dopant concentration maybe in the range of about 100 mM to about 10 M, which will result inabout 3% to about 30% incorporation of the Cu dopant or about 12% toabout 80% incorporation of the Sb dopant into the first portion of theplated Cu or Sb doped zinc-based semiconductor layer 210 during a firstportion of the plating process. In step 812, first heater 715 heats thefirst plating solution 720 to a predetermined temperature for depositionof the Cu or Sb doped zinc-based semiconductor layer 210, for example, atemperature in the range of about 10° C. to about 100° C. In step 813, apartially completed photovoltaic device 200 is contacted with the heatedfirst plating solution 720 in containing 710. In step 814, first powersource 770 generates a suitable ECD bias voltage, for example, in therange of about −0.3 V to about −10 V across the partially completedphotovoltaic device 200 and the first plating solution 720, which formsa first portion of the Cu or Sb doped zinc-based semiconductor layer 210over the partially completed photovoltaic device 200.

In step 815, a second plating solution 722 is prepared with a Cu or Sbdopant concentration that is different than the Cu or Sb dopantconcentration in the first plating solution 720. The second platingsolution may include a solvent, for example, water, a Cu or Sb dopantcompound dissolved in the solvent, a complexing agent, for example,citrate, dissolved in the water and a zinc-based semiconductor solutemixture dissolved in the water. To form a Cu or Sb doped zinc-basedsemiconductor layer 210 that is a Cu:ZnTe or Sb:ZnTe reflector layer150, the zinc-based semiconductor solute mixture may include, forexample, zinc, and telluride ions or electrolytes, as a solute dissolvedin the solvent, in a predetermined ratio for deposition of a Cu:ZnTe orSb:ZnTe reflector layer 150. To form a Cu or Sb doped zinc-basedsemiconductor layer 210 that is a Cu:CZT or Sb:CZT transition layer 145,the zinc-based semiconductor solute mixture may include, for example,cadmium, zinc, and telluride ions or electrolytes, as a solute dissolvedin the solvent, in a predetermined ratio for deposition of a Cu:CZT orSb:CZT transition layer 145. If the dopant concentration in the firstplating solution 720 was set to incorporated a high percentage of Cu orSb dopant into the first portion of the Cu or Sb doped zinc-basedsemiconductor layer 210, then the dopant concentration in the secondplating solution 722 may be set to incorporate a low percent of Cu or Sbdopant, for example, in the range of about 0.01 mM to about 100 mM,which will result in about 0.0001% to about 3% incorporation of the Cudopant or about 0.5% to about 12% incorporation of the Sb dopant intothe second portion of the plated Cu or Sb doped zinc-based semiconductorlayer 210 during the second portion of the plating process. If thedopant concentration in the first plating solution 720 was set toincorporated a low percentage of Cu or Sb dopant into the first portionof the Cu or Sb doped zinc-based semiconductor layer 210, then thedopant concentration in the second plating solution 722 may be set toincorporated a high percentage of Cu or Sb dopant, for example, in therange of about 100 mM to about 10 M, which will result in about 3% toabout 30% incorporation of the Cu dopant or about 12% to about 80%incorporation of the Sb dopant into the second portion of the plated Cuor Sb doped zinc-based semiconductor layer 210 during a second portionof the plating process. In step 816, second heater 717 heats the secondplating solution 722 to a predetermined temperature for deposition of aCu or Sb doped zinc-based semiconductor layer 210, for example, atemperature in the range of about 10° C. to about 100° C. In step 817,the partially completed photovoltaic device 200 is removed from thefirst plating solution 720 and contacted with a second plating solution722. In step 818, a second power source 774 generates an ECD biasvoltage, for example, in the range of about −0.3 V to about −10 V,across the partially completed photovoltaic device 200 and the secondplating solution 722.

Depositing the Cu or Sb doped zinc-based semiconductor layer 210 usingmultiple plating baths with different Cu or Sb dopant concentrations inthe different plating solutions changes the amount of the Cu or Sbdopant into the Cu or Sb doped zinc-based semiconductor layer 210 in astep-wise fashion. It should be noted that although steps 811-818describe using only two separate plating baths, any desirable number ofplating baths with different Cu or Sb dopant concentrations may be usedto provide the desired steps of Cu or Sb dopant incorporation into theplated Cu or Sb doped zinc-based semiconductor layer 210 and the stepsof distinct dopant incorporation into the plated Cu or Sb dopedzinc-based semiconductor layer 210 will correspond to the number ofbaths used in the plating process. In step 819, the partially completedphotovoltaic device 200 with the newly plated Cu or Sb doped zinc-basedsemiconductor layer 210 is removed from the second plating solution 722.Again, it should be noted that the steps 811-819 shown in FIG. 5describe the steps in ECD plating process 800, but do not necessarilyindicate any particular order or sequence of steps.

The embodiments described above are offered by way of illustration andexample. It should be understood that the examples provided above may bealtered in certain respects and still remain within the scope of theclaims. It should be appreciated that, while the invention has beendescribed with reference to the above exemplary embodiments, otherembodiments are within the scope of the claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. An electrochemical deposition systemcomprising: a first plating solution comprising a dopant, a complexingagent and a zinc-based semiconductor solute; and a first electrochemicaldeposition unit for forming at least a first portion of a dopedzinc-based semiconductor layer on a partially completed photovoltaicdevice placed in the first plating solution, wherein the firstelectrochemical deposition unit is configured to incorporate the dopantfrom the first plating solution into the doped zinc-based semiconductorlayer during a deposition process.
 2. The system of claim 1, wherein thedopant in the first plating solution is a Cu dopant or an Sb dopant. 3.The system of claim 1, wherein the complexing agent in the first platingsolution is at least one of citrate, phenathroline, thoicyanate,halides, pyridines or their derivatives.
 4. The system of claim 3,wherein the first electrochemical deposition unit comprises: a firstplating bath for containing the first plating solution, wherein thefirst plating solution is contacted with the partially completedphotovoltaic device; a first heater below the first plating bath forheating the first plating solution to a predetermined temperature; and apower source electrically connected to the partially completedphotovoltaic device for generating a bias voltage across the partiallycompleted photovoltaic device when it is in contact with the firstplating solution.
 5. The system of claim 4, wherein the semiconductorsolute comprises solutes of zinc (Zn) and telluride (Te).
 6. The systemof claim 4, wherein the dopant concentration in the first platingsolution is in the range of about 0.01 mM to about 10 M.
 7. The systemof claim 4, wherein the first heater is configured to heat the firstplating solution to a temperature in the range of about 10° C. to about100° C.
 8. The system of claim 4, wherein the power source is configuredto generate a bias voltage across the partially completed photovoltaicdevice and the first plating solution in the range of about −0.3 V toabout −3 V.
 9. The system of claim 4, wherein the doped zinc-basedsemiconductor layer is a doped zinc telluride layer or a doped cadmiumzinc telluride layer.
 10. The system of claim 4, wherein the firstelectrochemical deposition unit further comprises a first power controlunit coupled to the power source for adjusting the bias voltage acrossthe partially completed photovoltaic device and the first platingsolution.
 11. The system of claim 10, wherein the first electrochemicaldeposition unit is configured to change the amount of dopantincorporated into at least the first portion of the doped zinc-basedsemiconductor layer as it is formed on the partially completedphotovoltaic device by changing the bias voltage.
 12. The system ofclaim 11, wherein the first power control unit is configured to changethe bias voltage from a first set bias voltage to a second set biasvoltage during a predetermined period of time for forming at least thefirst portion of the doped zinc-based semiconductor layer on thepartially completed photovoltaic device.
 13. The system of claim 12,wherein the first power control unit is configured to change the biasvoltage in a step-wise or in a gradual fashion.
 14. The system of claim4, further comprising: a second plating solution comprising a dopant, acomplexing agent and a zinc-based semiconductor solute, wherein thesecond plating solution has a different composition than the firstplating solution; and a second electrochemical deposition unit forforming a second portion of the doped zinc-based semiconductor layer onthe partially completed photovoltaic device placed in the second platingsolution, wherein the second electrochemical deposition unit isconfigured to incorporate the dopant from the second plating solutioninto the doped zinc-based semiconductor layer during the depositionprocess.
 15. The system of claim 14, wherein the second electrochemicaldeposition unit comprises: a second plating bath for containing thesecond plating solution, wherein the second plating solution iscontacted with the partially completed photovoltaic device; a secondheater below the second plating bath for heating the second platingsolution to a predetermined temperature.
 16. The system of claim 15,wherein the power source is electrically connected to the partiallycompleted photovoltaic device for generating a bias voltage across thepartially completed photovoltaic device when it is in contact with thesecond plating solution.
 17. The system of claim 16, wherein the dopantconcentration in the first plating solution is different than the dopantconcentration in the second plating solution.
 18. The system of claim17, wherein the first and second plating solutions further comprisesolutes of zinc (Zn) and telluride (Te).
 19. The system of claim 17,wherein the first and second heaters are configured to heat the firstand second plating solutions to a temperature in the range of about 10°C. to about 100° C.
 20. The system of claim 17, wherein the power unitis configured to generate a bias voltage across the partially completedphotovoltaic device and the first and second plating solutions in arange of about −0.3 V to about −3 V.